Passport 2 and Passport 2LT Service Manual Rev AG Dec 2008

S e r v i ce M a n u a l

Datascope

Passport® Datascope

Passport®

FilterLine® is a U.S. registered trademark of Oridion Medical Ltd. Masimo SET® is a U.S. registered trademark of Masimo Corp. MediCO2® is a registered trademark of Oridion Medical Ltd. miniMediCO2® is a registered trademark of Oridion Medical Ltd. Microstream® is a U.S. registered trademark of Oridion Medical Ltd. Navigator™ is U.S. trademark of Mindray DS USA, Inc. Nellcor® is U.S. registered trademark of Nellcor Puritan Bennett Inc. OxiMax® is a U.S. registered trademark of Nellcor Puritan Bennett Inc. Oxismart® is a U.S. registered trademark of Nellcor Puritan Bennett Inc. Passport 2® is a U.S. registered trademark of Mindray DS USA, Inc. PatientNet® is a U.S. registered trademark of GE Medical Systems Information Technologies. Velcro® is a registered trademark of Velcro Industries B.V. Visa® is a U.S. registered trademark of Mindray DS USA, Inc.

Copyright © Mindray DS USA, Inc. 2008. Printed in U.S.A. All rights reserved.Contents of this publication may not be reproduced in any form without permission of Mindray DS USA, Inc.

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Table of Contents

Contents ... v Foreword ... v Note ... v Warning... v

Operation... 1 - 1 Introduction ... 1 - 1 Controls, Indicators And Connectors ... 1 - 2 Operation... 1 - 2

Theory of Operation ... 2 - 1 CPU Control Module ... 2 - 2 MPC860T Host CPU, U2 ... 2 - 2 Serial Communications Channels... 2 - 2 Fast Ethernet Controller... 2 - 3 Power-On Reset, U14... 2 - 3 Flash Memory, U3, U4, U5, U6, U180, U181, U182, U183 ... 2 - 3 DRAM Memory, U8, U10... 2 - 4 RTC with CPU Supervisor... 2 - 4 Battery Backup SRAM, U9 ... 2 - 5 Dual Port RAM, U604, U777... 2 - 5 Audio Generator Circuit, U12, U27, U13 ... 2 - 5 Module ID, U44 ... 2 - 6 Tone Generator, U39... 2 - 7 LCD/CRT VGA Controller, U16... 2 - 7 PCMCIA Interface... 2 - 7 Serial EEPROM ... 2 - 7 CO Interface Connector, J4 ... 2 - 8 Recorder Interface ... 2 - 8 CO2 Interface Connector, J23... 2 - 8 NIBP Interface Connector, J25 ... 2 - 8 Defib Connector, J24 ... 2 - 8 SYNC Connector, J22... 2 - 9 Docking Connector, J9 ... 2 - 9 3.3 Volt Power ... 2 - 9 -12 Volts DC ... 2 - 9 Communications Processor and Support ... 2 - 9 D/A Analog Outputs... 2 - 10 Analog Inputs... 2 - 10 SRAM ... 2 - 10 Keypad and Rotary Knob ... 2 - 10 Control Functions... 2 - 11 Module Bus ... 2 - 11 Front End Module ... 2 - 12 Power Supply... 2 - 12 Communication Isolation ... 2 - 12 Data Acquisition... 2 - 12 Analog to Digital Converter ... 2 - 13 Microcontroller and Data Processing... 2 - 13 Memory ... 2 - 14 I/O Ports and Software Register Programming ... 2 - 15 Signal Acquisition... 2 - 16 Lead Fault Detection... 2 - 16 Pacer Pulse/Electrosurgical Interference Detection... 2 - 17

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Respiration ... 2 - 17 Invasive Blood Pressure ... 2 - 18 Temperature... 2 - 19 Timers ... 2 - 19 Data Packets ... 2 - 20 TFT Display / Monochrome Interface Board and Keypad Board (P/N 0670-00-0686 or 0670-00-0726)... 2 - 21 The EPLD Interface to the CPU Board VIA SPI ... 2 - 21 Video display connections ... 2 - 21 TFT Inverter Connection ... 2 - 21 Speaker connection ... 2 - 21 Encoder connection ... 2 - 21 NIBP Module (P/N 0997-00-0501) ... 2 - 22 Pneumatic System Control... 2 - 22 Pressure Transducer, PT1 ... 2 - 23 Pressure Transducer, PT2 ... 2 - 23 Over-Pressure Detection... 2 - 23 Pump, M1 ... 2 - 24 Dump Valve, V1 ... 2 - 24 Linear Valve, V2... 2 - 24 Primary Microcontroller, U10 ... 2 - 25 Secondary Microcontroller, U4 ... 2 - 25 Memory ... 2 - 26 CMOS Static RAM... 2 - 26 CMOS EEPROM... 2 - 27 Voltage Sources ... 2 - 27 Host Reset... 2 - 28 Patient Connector Board AAMI... 2 - 29 Spark Gap Suppressor ... 2 - 29 Neon Bulbs... 2 - 29 Low-Pass Filter ... 2 - 29 EMI Suppressor ... 2 - 29 Patient and Power Isolation ... 2 - 29 Provide mating for ECG, Temperature and two IBP connectors ... 2 - 29 0670-00-0682-01 ... 2 - 30 0670-00-0682-02 ... 2 - 30 Patient Connector Board H.P. ... 2 - 31 Spark Gap Suppressor ... 2 - 31 Neon Bulbs... 2 - 31 Low-Pass Filter ... 2 - 31 EMI Suppressor ... 2 - 31 Patient and Power Isolation ... 2 - 31 Provide Mating for ECG, Temperature and two IBP connectors... 2 - 31 0670-00-0680-01 ... 2 - 32 0670-00-0680-02 ... 2 - 32 Nellcor/Interface Board... 2 - 33 Recorder Interface Board (AR-42)... 2 - 33 Detailed Description... 2 - 33 XE-50 Recorder Interface Board ... 2 - 34 Cooling Fault ... 2 - 34 Fan-Fault Sense ... 2 - 34 Power Filtering ... 2 - 34 XE-50 Interface... 2 - 34

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5V Regulator (U4)... 2 - 35 Power Supply ... 2 - 36 Part Numbers 0014-00-0250 and 0014-00-0190-01 ... 2 - 36 Part Number 0014-00-0251... 2 - 37 Communication Isolation... 2 - 39 El Display Interface Board ... 2 - 40 Overview ... 2 - 40 Detailed Description... 2 - 40 Passport 2 Passive Display/Keypad Interface Board... 2 - 41 Overview ... 2 - 41 Detailed Description... 2 - 41 NEC 10.4” Display/Keypad Interface Board ... 2 - 43 Video Display Interface ... 2 - 43 TFT Inverter Interface ... 2 - 43 Speaker Interface ... 2 - 44 Encoder Interface ... 2 - 44 The CPLD Interface to the CPU Board VIA SPI ... 2 - 45 Passport 2 NIBP Module (P/N 0670-00-0730 or 0670-00-0746-01)... 2 - 46 Pneumatic System Control... 2 - 46 Pressure Transducer, PT1 ... 2 - 47 ADC, U2 ... 2 - 47 DAC ... 2 - 48 Pump, M1 ... 2 - 48 Dump Valve, V1 ... 2 - 48 Linear Valve, V2... 2 - 48 Over-Pressure Detection... 2 - 49 Pressure Transducer, PT2 ... 2 - 50 12VSW Circuitry, Q1, Q2 ... 2 - 50 Primary Microcontroller, U10 ... 2 - 50 Secondary Microcontroller, U4 ... 2 - 51 Memory ... 2 - 52 CMOS Static RAM, U5 ... 2 - 52 CMOS EEPROM, U9 ... 2 - 52 Hardware Locks ... 2 - 53 Reset... 2 - 53 Host Reset... 2 - 53 SpO2 Interface Board (Nellcor, Nell-3™ and Masimo)... 2 - 54 Power Supply ... 2 - 55 SpO2 UART Serial Interface ... 2 - 56 Panel Interface Extension Connector... 2 - 56

Repair Information ... 3 - 1 Introduction ... 3 - 1 Safety Precautions... 3 - 1 Troubleshooting Guidelines ... 3 - 7 Exchange Programs ... 3 - 7 Special Tools Required ... 3 - 7 Disassembly Instructions... 3 - 8

Assembly and Schematic Diagrams... 4 - 1 Replacement Parts ... 5 - 1 Parts List Front Housing ... 5 - 5 Parts List Rear Housing... 5 - 15 Communication Ports Parts List ... 5 - 25

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Calibration Procedure ... 6 - 1 Calibration Introduction ... 6 - 2 Warning and Guidelines ... 6 - 2 Test Equipment and Special Tools Required... 6 - 2 Description ... 6 - 2 Diagnostics ... 6 - 3 Diagnostic Test Menu ... 6 - 3 Keypad / Control Knob Test ... 6 - 4 Recorder Test ... 6 - 5 Display Tests ... 6 - 6 Pixel Test ... 6 - 6 Color Test ... 6 - 7 NIBP Tests ... 6 - 8 Verification ... 6 - 17 Initial Set-up ... 6 - 17 ECG Tests... 6 - 18 IBP 1 and IBP 2 Verification ... 6 - 20 Temperature Verification... 6 - 20 SpO2 Verification ... 6 - 20 NIBP Verification ... 6 - 21 Battery Operation Verification ... 6 - 21 CO2 Operation Verification... 6 - 21 Leakage Current Tests ... 6 - 21

Preventive Maintenance... 7 - 1 Preventive Maintenance Schedule ... 7 - 2 Mechanical / Physical / Visual Inspection ... 7 - 2 Perform at Twelve Month Intervals... 7 - 2 Preventive Maintenance Kit ... 7 - 2 Perform Verification and NIBP Calibration – Annually ... 7 - 2 Perform Verification and CO2 Calibration – Annually... 7 - 2 User Preventive Maintenance Introduction ... 7 - 2 Care And Cleaning Of The Monitor ... 7 - 3 Care and Cleaning of SpO2 Sensor ... 7 - 3 Cleaning CO2 Sensors, Adapters And Sampling Components... 7 - 3 Sterilization and Cleaning of Reusable Cuffs ... 7 - 4 Battery Replacement and Maintenance ... 7 - 4 Battery Replacement ... 7 - 4 Battery Maintenance ... 7 - 4 Recorder Paper Replacement... 7 - 5 Care and Storage of Thermal Chart Paper ... 7 - 5 How to Get Help ... 7 - 6 References ... 7 - 7 Warranty... 7 - 9 USA, Canada, Mexico, and Puerto Rico... 7 - 9 International (excluding North America) ... 7 - 10 Manufacturer’s Responsibility ... 7 - 11 Extended Warranty... 7 - 11

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Contents

Introduction

Contents Chapter 1.0 Operation ... 1-1 2.0 Theory of Operation ... 2-1 3.0 Repair Information ... 3-1 4.0 Assembly and Schematic Diagrams ... 4-1 5.0 Replacement Parts ... 5-1 6.0 Calibration Procedure ... 6-1 7.0 Preventive Maintenance ... 7-1

Foreword This Service Manual is intended as a guide for technically qualified personnel during repair and calibration procedures. The information has been divided into the eight chapters listed above. A detailed table of contents is provided on the first page of each chapter. This publication may have been updated to reflect product design changes and/or manual improvements. Any such changes to this manual would be accomplished by supplying replacement pages and instructions for inserting or affixing them into the manual.

Note Unauthorized servicing may void the remainder of the warranty. Check with the factory or with a local authorized representative to determine the warranty status of a particular instrument.

Warning The Passport 2 operates on line voltages. Therefore, an electric shock hazard may exist when the instrument covers are removed. Repair and calibration procedures should only be performed by qualified personnel who proceed with care and follow proper servicing techniques. Warnings are given in Chapters 4 and 7, as well as in other appropriate locations.

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Operation

1.1 Introduction ... 1-1 1.2 Controls, Indicators And Connectors ... 1-2 1.3 Operation ... 1-2

1.1

Introduction Sections 1.2 and 1.3 are intentionally left blank. Please refer to the Operating Instructions for complete details.

OPERATING INSTRUCTIONS

PART NUMBER

For software version V.x & earlier Domestic

0070-00-0440-01

International

0070-00-0440-02

For software version V.x & later

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1-1

Controls, Indicators And Connectors

1.2

Operation

Controls, Indicators And Connectors THIS SECTION LEFT INTENTIONALLY BLANK. REFER TO THE OPERATING INSTRUCTIONS.

1.3

Operation THIS SECTION LEFT INTENTIONALLY BLANK. REFER TO THE OPERATING INSTRUCTIONS.

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Theory of Operation

2.1 CPU Control Module ... 2-2 2.2 Front End Module ... 2-12 2.3 TFT Display / Monochrome Interface Board and Keypad Board (P/N 0670-00-0686 or 0670-00-0726) ... 2-21 2.4 NIBP Module (P/N 0997-00-0501) ... 2-22 2.5 Patient Connector Board AAMI ... 2-29 2.6 Patient Connector Board H.P. ... 2-31 2.7 Nellcor/Interface Board ... 2-33 2.8 Recorder Interface Board (AR-42) ... 2-33 2.9 XE-50 Recorder Interface Board ... 2-34 2.10 Power Supply ... 2-36 2.12 El Display Interface Board ... 2-40 2.13 Passport 2 Passive Display/Keypad Interface Board ... 2-41 2.14 NEC 10.4” Display/Keypad Interface Board ... 2-43 2.15 Passport 2 NIBP Module (P/N 0670-00-0730 or 0670-00-0746-01) ... 2-45 2.16 SpO2 Interface Board (Nellcor, Nell-3™ and Masimo) ... 2-54 2.17 Power Supply ... 2-55 2.18 SpO2 UART Serial Interface ... 2-56

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CPU Control Module

2.1

Theory of Operation

CPU Control Module Overview This board has the main program and system controller for the Passport 2. It also contains the Communications Coprocessor, PCMCIA interface, RTC, Audio, CRT/LCD controller, Serial Channels and module bus interface connectors.

2.1.1

MPC860T Host CPU, U2 Device U2, is a MPC860T Microcontroller, which contains a PowerPC core, 32 bit address and data bus, Memory Controller (8 banks), general purpose timers, System Integration Unit (SIU), Multi-Level Interrupts, Communications Processor module, SPI port, 100 Mbit Ethernet Controller, and a Dual PCMCIA interface. Clock oscillator Y1, 5 Mhz, is multiplied by the MPC860T's PLL circuit to achieve the 45MHz for Passport 2. There are six serial channels, of which five are used. Two are full RS-232 compliant and are used for external communications: one is used for the Recorder module; one is used to connect to the Instrument Radio; and one is used for the Audio Synthesizer which goes to the Keypad/ Display connector. There are eight programmable chip select/wait state control groups, only six are used. They are listed below. The power-on reset to the microcontroller is generated by U14, MAX814L CPU Supervisor. The signal generated is active low for 140ms. PORESET* is generated whenever both VCC rises from 0 to 4.75 volts and the 3.3V rises from 0 to 2.75V. The PORESET* signal is distributed to other components that require a power on reset by using a spoke distribution with series resistors instead of a daisy chain to better balance the signal paths. The U1 CPLD in turn generates a HRESET* signal and a buffered BRESET* signal that is used to reset all external components that require a reset other than PORESET*. All high speed clock signal and control lines have series terminating resistors to reduce EMI.

2.1.2

Serial Communications Channels There are four serial communications channels called SCC's that are part of the MPC860T's Communication Processor Module. The following describes the function of each of them. SCC1 - This channel is assigned to external communication use. It is buffered (U49) to RS232 levels before connection to the docking connector which is part of the base station or comm-port system. SCC1 will operate in the standard UART mode with all hardware control lines available. SCC2 - This channel is assigned to external communication use. It is buffered (U50) to RS232 levels before connection to the docking connector which is part of the base station or comm-port system. SCC2 will operate in the standard UART mode with all hardware control lines available. SCC3 - This channel is assigned to the Instrument Radio on connector J15.

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CPU Control Module

SCC4 - This channel is assigned to the serial Recorder. It operates at 3V logic levels and is connected to Recorder Connector J8. SCC4 will operate in the standard UART mode with all hardware control lines available. There are two Serial management Channels called SMC's that are part of the MPC860T's Communication Processor Module. The following describes the function of each of them. SMC1 - Not used. Pins used as general purpose I/O. SMC2 - This channel is assigned to Audio. The audio circuit is composed of three integrated circuits, Wave Table Music Synthesizer, a 24 Bit Stereo D/A Converter and a one watt Power Amplifier. It operates at 3V logic levels and is connected to the Keypad/Display J5. SMC2 will operate in the standard UART mode with no hardware control lines available.

2.1.3

Fast Ethernet Controller The MPC860T includes a 10/100 BASE-T Ethernet channel. The fast Ethernet Controller is implemented independently providing fast Ethernet connectivity without effecting the performance of the CPM. Full duplex 100 Mbps operation is supported at a system clock of 45 Mhz and higher. A 25 Mhz system clock supports 10 Mbps operation or half duplex 100 Mbps operation.

2.1.4

Power-On Reset, U14 The Power-On reset signal is created by components U14, R1, R12, R13 and Q4. The active low power-on reset signal required by the MPC860T, as well as other components that require reset, is generated for both logic voltages 5V and 3.3V. This keeps the CPU in reset until the power for all the digital components are above minimum operating levels. The reset signal PORESET is distributed in a spoke pattern with the following references, PORESET*, POREST2*, PORESET3*, PORESET4*, and PORESET5*. The duration of the power-on reset signal is 140ms min. The MPC860T requires only 3us minimum after power is stable and all other components that receive this reset require less than 1ms.

2.1.5

Flash Memory, U3, U4, U5, U6, U180, U181, U182, U183 Program code is stored in eight flash memory devices configured as 2M x 32 bytes in 2 banks for a total of 16 Mbytes. These devices allow for in circuit programming via the MPC860T background debug mode (BDM). There are no special programming voltages, programming is done using the existing 3.3Volts. This is one way to allow for initial factory programming as well as software upgrades. Alternately a boot loader can be programmed into the flash parts using the BDM, and the initial software and all upgrades can be programmed into the flash by the boot loader from a PCMCIA memory card. The Flash devices are configured and connected to the processor in the byte mode. The specified access time for the Flash devices is 90nsec and will therefore require 4 wait states. Upon reset, the MPC860T provides a boot chip select CS(0) which is hard wired to the flash memory to allow boot of the operating software. The board support software must execute prior to any other external or internal hardware, in order to function properly.

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Theory of Operation

The Flash devices are provided a buffered reset by FET Q9 and associated components. This reset signal is generated from the MPC860T's HRESET. The reset is required to place the Flash devices' internal state machine in a known state after power is applied for either fetching or programming. Bank decoding is performed by a sub-circuit of CPLD U1, and is dependent on the state of Address line A(8) in conjunction with active CS0*.

2.1.6

DRAM Memory, U8, U10 This memory is made up of two 4M x 16 devices which form a 4M x 32 byte memory array. These memories are volatile as well as requiring special timing and control signals, RAS* and CAS* to operate. The type of DRAM is Fast Page Mode with an access time of 50nsec. The special timing signals required are generated by an internal timing circuit contained in the MPC860T. This timing generator is called Universal Programmable Machine A (UPMA). There is another one called Universal Programmable Machine B (UPMB), which is not used. The universal programmable machines are flexible interfaces that connect to a wide range of memory devices, such as Fast Page Mode Dram's. At the heart of the UPM is an internal memory RAM that specifies the logical value driven on the external memory controller pins for each clock cycle. Each word in the RAM array provides bits that allow a memory access to be controlled with a resolution of one quarter of the external bus clock period on the byteselect and chip-select lines. The RAM array contains 64, 32 bit words. The internal signal timing generator loads the RAM word from the RAM array to drive the general-purpose lines, byte-selects, and chip-selects. The UPM RAM array is to be loaded by the board support software at power-on. The following is UPM RAM array values to support 50nsec Fast Page Mode DRAM with the processor operating at 50MHz. UPMA Initializations for 50nsec DRAM's @ 50Mhz.

2.1.7

RTC with CPU Supervisor The Real Time Clock module, BQ4847, integrates a time of day clock, a 100 year calendar, a CPU supervisor, a battery and a crystal in a 28 pin DIP module. There are 16 registers which contain real-time clock and alarm functions. The clock has an accuracy of +/-1 minute per month. The duration of the power-on reset signal is 100ms min. The MPC860T requires only 3us minimum. Using the BQ4747’s CE out and battery voltage out, Vout, static RAM U9 is made to be nonvolatile. The internal battery powers the real time clock and maintains SRAM information in the absence of system voltage. When an out of tolerance (4.3 to 4.5 volt) condition is detected the BQ4747 generates an interrupt warning. The interrupt is fed to the IRQ0 NMI input on the MPC860T. This will allow 90us min. to save any data to the non-volatile SRAM.

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2.1.8

CPU Control Module

Battery Backup SRAM, U9 The SRAM is configured as 128K x 8 bits and is used to store system configuration settings. These settings are required to be non-volatile, therefore the SRAM is battery backed-up when system power is removed. This is achieved by the battery output that is contained in the RTC module, U7, and is outputted on pin 1.

2.1.9

Dual Port RAM, U604, U777 There is a high speed 2K x 8 Dual Port RAM with internal logic for inter-processor communications. The device has two independent ports with separate control, address, and I/O pins that permit independent asynchronous access for reads to any location in memory. However, an attempt by one of the processors to access ('READ' or 'WRITE') an address location at the same time the other processor is attempting to access the identical location results in a 'BUSY' condition, and results in a 'write inhibit' to whichever side asserted the chip enable last (Not all such accesses will be 'WRITE LEFT/WRITE RIGHT'). The 'BUSY' condition is not reported to either processor in this implementation, and therefore, the software must be designed so as to avoid the possibility of concurrent access by both processors to an identical location. The device is used for inter-communication between the main processor, MPC860T (U2) and the communication processor MCF5282 (U22). Refer to the Module Bus Protocol Specification (See Appendix). The implementation uses the interrupt function. There are two flags, one for each side of the DPRAM. A memory location within the DPRAM is assigned to each flag. The interrupt line to the MPC860T is asserted when the MCF5282 writes to memory location CS1 + 0x0000 07FE. In order to reset this interrupt flag, the MPC860T must access memory location CS3 +0x0000 0FFE. Similarly, the interrupt line to the MCF5282 is asserted when the MPC860T writes to memory location CS3 + 0x0000 0FFF. In order to reset this interrupt flag, the MCF5282 must access memory location CS1 + 0x0000 07FF. Please note that in addition to the flag functions described above, these two addresses are valid memory locations and may be used for message passing. A 5V to 3.3V conversion is performed with U777. This is to protect the DPRAM, which cannot have 5V logic on any of its pins, even if it is not accessing the bus.

2.1.10

Audio Generator Circuit, U12, U27, U13 The audio circuit is composed of three integrated circuits, Wave Table Music Synthesizer, a 24 Bit Stereo D/A Converter and a one watt Power Amplifier. U12 is a complete general MIDI wave table synthesizer on a single integrated circuit. The MIDI interpreter, synthesis engine, effects processing, and all memory are included on chip. The device receives a standard serial MIDI data stream at 31.25 +/-1% kbits/s, and outputs a stereo 16 bit digital audio stream at 44.1kHz.

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Theory of Operation

The digital outputs LRCLK and SOUT from the U12 provide the clock and the digital audio data input to the stereo D/A converter. This is a complete stereo digital to analog system including digital interpolation, 128X third order delta-sigma D/A conversion, digital deemphasis and analog filtering. The de-emphasis circuit is not used in this application. The stereo outputs from the U27 are summed together and is fed to the power amplifier U13, which is a bridge connected audio power amplifier capable of delivering 1watt of continuous average power to an 8 ohm speaker load. The circuit is optimized for a frequency range of 100Hz to 10KHz.

2.1.11

Module ID, U44 There is a Module ID port implemented by U44 that is used to read the ID code from any device that is connected to Docking connector, J9. These devices can be either a Base Station or Comm Ports. Each of these devices has a unique code. The base station is hot swappable, while the Comm Ports are not hot swappable. When any base station is connected or removed from the Docking connector J9 using live insertion, an interrupt IRQ4* is generated. When a Comm Port, which is not hot swappable, is powered up with a Passport 2 monitor, the module ID is read by software, and is in the flow of the start-up code. This reading of the module ID upon power up is automatic and is not dependent on whether there is an IRQ4* or not, or if a base station or Comm Port is connected. Therefore a duplicate IRQ4*, which may be generated by the modules upon power up, is redundant. This IRQ4* interrupt is falling edge triggered and can be sourced only when IRQB* is previously low and IRQA* then follows and goes low. The state diagram for the IRQA* / IRQB* logic is such that IRQB* must be low prior to an IRQA* falling edge. In the Comm Ports, IRQB* is tied to GND and IRQA* is driven low after the circuitry becomes active, thus the condition is met. In the base station, IRQB* is driven low whenever there is power applied to the base station, and IRQA* is driven low whenever the base station is powered AND the monitor's 3.3V power is within regulation, again, meeting the condition. IRQA* and IRQB* (on J9-17, J9-67) are both generated external to the CPU board. Components involved in the state control logic on the CPU board, affecting the rise time of IRQA* and IRQB*, are components R185, R174, C427, and D9. U64 is used to generate IRQ4*. The signal that enables U44 to drive the Module ID field onto the data bus is MODIDCS*, active low. It is generated by a sub-circuit of CPLD U1 by decoding Address lines A[18:20] in conjunction with an active CS3*.

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2.1.12

CPU Control Module

Tone Generator, U39 The tone generator is implemented using an eight bit microcontroller. The device generates a tone signal of 909Hz for a duration of 300ms. The tone is generated in response to the following input conditions: 1. When the system is first turned on, the level of the MPC860T's BRESET* (same as HRESET*) signal is monitored. If this level is detected as high, the tone is generated. 2. When an active low status signal input is detected, the tone is generated. The status signal tone 769Hz for a duration of 300ms is generated by the MPC860T on Port A, bit 4 (PA4). The signal can be repeated as required in order to create a series of tones.

2.1.13

LCD/CRT VGA Controller, U16 The LCD/VGA controller is a SPC8110 with an integrated RAMDAC, PLL Bit Block Transfer engine and a VL Local Bus interface. It is capable of displaying 256 colors. Support for video modes of 640 X 480 and 800 X 600 is required. The display controller needs to be able to drive a TFT color LCD (10.4" or 12.1") (single scan), or EL panel (dual scan), or Monochrome LCD Passive (dual scan) and an external VGA color CRT simultaneously. The display system consists of the LCD/CRT VGA controller (U16), clock oscillator (U65), the programmable clock synthesizer (Y2 & U66), and video display RAM (U18 & U19). The signals required by the various display panels are routed to the Keypad/Display board through connector J5. The various Keypad/Display boards have specific interface connectors for each display type, requiring only a simple one-to-one cable assembly. The display panel identifies itself to the CPU module by connecting selected pins in the VIDSEL[4:1] field directly to the power net. These signals are pulled down to 3VGND on the CPU module through 33.2K resistors, and their assigned value is then read, in order to identify the panel type.

2.1.14

PCMCIA Interface The PCMCIA interface is a dual interface called Socket A and Socket B. The PCMCIA cards plug into a dual stacked connector assembly, J14. The MPC860T's PCMCIA host adapter module provides all the control logic for each PCMCIA socket interface and requires only power switching logic and buffering. The additional external buffering allows the PCMCIA host adapter module to support up to two PCMCIA sockets and provide electrical isolation. Because the PCMCIA interface specification was designed around the Intel (Little Endian) method of storing 16 bit words, a byte swapping scheme had to be employed in order to conform to the standard. Motorola follows the Big Endian method.

2.1.15

Serial EEPROM The memory is made up of 512 bytes of non-volatile memory. U45 is a dip part and is socketed to allow programming the memory with an external programmer. This device is used to store network settings. Communications from the device is done via the MPC860T's SPI interface. To select this SPI device the MPC860T's, SPISEL signal (PB31) should be set to logic '0'.

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CPU Control Module

2.1.16

Theory of Operation

CO Interface Connector, J4 This connector connects the Communications Processor Module Bus to the External Parameter Module. In addition power (+5Vdc and +12V2) and ground are provided. The digital signals are protected from ESD by capacitors C489 to C494.

2.1.17

Recorder Interface The recorder interface (J8) is a serial interface which is 8 bit, 1 stop bit, no parity and a baud rate of 38.4K. The recorder interface is implemented using the MPC860T SCC4. The recorder is controlled by sending a series of software commands along with data over the serial interface. The recorders electronics process the incoming commands and data and send print information to the print head. Hardware handshaking is provided using the RTS*/CTS* control lines. Handshaking signals are used to control the transmission of data to the recorder and to ensure that the MPC860T does not send another command until the current one has been processed. The RECRST* signal is used to reset the recorder. This signal is an active low output from PB(16) of the MPC860T and is a software control function. There is an additional signal which is located on the connector, IRQ3*, which indicates when data can be sent. This connector also provides an interface to the fan for control and monitoring. There is a control line from the MPC860T to turn the fan on or off and a status signal that indicates if its functioning.

2.1.18

CO2 Interface Connector, J23

This connector connects the Communications Processor Module Bus to the external CO2 module. In addition power (+5 Vdc and +12V2) and ground are provided. The digital signals are protected from ESD by capacitors C136 to C139.

2.1.19

NIBP Interface Connector, J25 This connector connects the Communications processor module bus to the external NIBP module. In addition power (+5 Vdc, +12V2) and ground are provided.

2.1.20

Defib Connector, J24 This connector provides the interface to an external Defibrillator. SMC1 is provided if serial communications is necessary. There is a provision to accept a logic signal that is monitored by input PB(14) on the MPC860T. There is a provision for an analog input signal that is fed to the 10 bit A/D converter that is contained with the Communication processor (916X1). In addition there is a re-created analog output (ECG_OUT) of the ECG waveform and a ECG_SYNC signal which is the E trigger from the front end electronics. The ECG_SYNC signal which is the E trigger from the front end electronics or ECG_SYNC created by the 12 lead communications data from the Mortara card within the MPC860T. The source is controlled by the MPC860T. All signals are filtered with T-Pole filter devices.

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Passport 2®/Passport 2 LT™ Service Manual

Theory of Operation

2.1.21

CPU Control Module

SYNC Connector, J22 This connector provides the interface to an external device. There is a provision for an analog input signal that is fed to the 10 bit A/D converter that is contained with the Communication processor (916X1). In addition there is a re-created analog output (ECG_OUT) of the ECG waveform and blood pressure (IBP_OUT).

2.1.22

Docking Connector, J9 The docking interface connector provides the interface between the CPU Control module and the Base Station or a Comm-Port. The main purpose of the Base Station or Comm-Port is to provide interface connectors and some interface circuitry that is not part of the CPU Control module. It is not feasible or practical to include all the connectors on the CPU Control module itself. The signal groups that are part of the docking interface are shown in the table below:

2.1.23

3.3 Volt Power The 3.3 Vdc is generated by Synchronous Step-Down Power Supply Controller U47 (MAX767) and associated discrete components. The input to the power supply controller is +5 Vdc and its output is +3.3 Vdc +/-5% at 750ma. The controller operates a frequency of 300 Khz. The current sense resistor (R32) is connected to the controller using a Kelvin connection (no current flow in sense lines). The current limit is controlled by current sense resistor R32.

2.1.24

-12 Volts DC There is a limited requirement for -12 Vdc @ 30 ma max. The supply voltage was created by using power inverter U51 (LTC1144) operating at 10KHz. This device takes the +12V1 as an input and generates -12 Vdc +/- 10% as an output. The -12 Vdc is used by RS-232 buffers U49 and U50 as well as Op-Amp U101.

2.1.25

Communications Processor and Support The Communications Processor is U22, a Motorola MCF5282 microcontroller operating in master mode. The board pulls CPRCON* low, which causes the processor to enter this mode as it comes out of reset. The internal 64.0 MHz clock is generated by the internal synthesizer from a 8.000 MHz reference crystal, Y600. The crystal operates with roughly sinusoidal waveforms, and therefore generates less EMI than a square-wave oscillator module. To further minimize EMI and avoid the need for external pull up resistors, all unneeded dynamic I/O pins are set as outputs and disabled. This is performed at initial software boot up. This also helps reduce power dissipation. The purpose of the Communications Processor is to communicate with Passport 2 measurement modules such as NIBP, Front End, etc. The communications is handled over a RS-485 module bus, where the Communications Processor is the master and everyone else is a slave. This processor also handles scanning the front panel keypad, rotary knob, and updating its LEDs.

Passport 2®/Passport 2 LT™ Service Manual

0070-10-0441

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